1. Field of the Invention
The invention relates to a method for forming a bottom electrode, and more particularly to a method for forming bottom electrodes of trench capacitors using uniform mask layers.
2. Description of the Related Art
Data is stored in a DRAM by electric charges in a capacitor of a memory cell. Greater capacitance means more chargers are stored in a capacitor. Therefore, in a larger capacitor, the data is less affected by noise, such as soft errors resulting from foreign particles, and the data stored in the capacitor is more stable.
Reducing the size of individual semiconductor devices to increase their density on an integrated circuit (IC) chip is a topic of great interest to those skilled in the art. This reduces chip size and power consumption, and enables faster chip operation. In order to achieve a memory cell with reduced size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, shorter gate length will result in higher leakage current that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the amount of charge stored on a storage capacitor, and thus requires a larger capacitance to ensure that stored charges are correctly detected.
Presently high density memory includes a stack capacitor and a deep trench capacitor, wherein the deep trench capacitor is formed in a trench deep in a substrate, and the volume on the surface of the substrate is less than the stack capacitor.
U.S. Pat. No. 4,353,086 teaches a complicated method for forming a conventional deep trench capacitor.
FIG. 1a is a top view of a deep trench array of a conventional DRAM, and FIG. 1b is a cross-section at line BB in FIG. 1a. 
In FIG. 1a, a channel and S/D of a MOS is formed in an active area 102, and a plurality of gates 104 is arranged perpendicular to a bit line 106. Pairs of deep trenches 112 are formed in an adjoining terminal of each adjoining active area 102. A dotted line 108 is a memory cell. A dotted line 138 acting as a contact to electrically connect the bit line 106 and the S/D.
In FIG. 1b, a p+ type silicon substrate 101 is provided, and a p+ type wall layer 122 is formed thereon, and an n+ type buried layer 120 is formed under the p+ type wall layer 122. The deep trenches 112 are deeply etched into the silicon substrate 101 at a predetermined depth through the p+ type wall 122 and the n+ type buried layer 120. An n+ type diffusion layer 114 is formed as an electrode around a bottom portion of the deep trenches 112. An ON dielectric layer 116 is formed on a sidewall and a bottom surface of the deep trench 112 bottom. The bottom portion of the deep trench 112 is filled with a first poly layer 118 as a storage node. A collar oxide layer 124 is formed on a sidewall of a top portion of the deep trench 112. The top portion of the deep trench 112 is filled with a second poly layer 126. A third poly layer 128 is formed as a buried strap on a top surface of the deep trench 112 to electrically connect the deep trench capacitor and a diffusing area 134 as S/D. A STI structure 130 is formed between the deep trenches 112 each other. The contact 138 is formed between the gates 104 electrically connect the bit line 106 and the S/D 134.
FIGS. 2a to 2i are cross-sections of the conventional method for forming a bottom electrode of a trench capacitor.
In FIG. 2a, a semiconductor substrate 201 having a dense trench area 21 and a less dense trench area 22 is provided. A pad oxide layer 202, a pad nitride layer 203, a borosilicate glass (BSG) layer 204, and a photoresist layer 205 with a plurality of openings 206 are sequentially formed on the semiconductor substrate 201. Portions of the BSG layer 204 are exposed via the openings 206 to define trenches described in the following.
In FIG. 2b, the exposed BSG layer is etched using the patterned photoresist layer 205 as an etching mask to form a plurality of openings 207 to expose portions of the pad nitride layers 203. The photoresist layer 205 is removed.
In FIG. 2c, the pad nitride layer, the pad oxide layer, and the semiconductor substrate 201 are an isotropically etched using the BSG layer 204 as an etching mask to form a plurality of trenches 208 as the semiconductor substrate 201. The BSG layer is removed. After the anisotropic etching, there are more trenches 208 in the dense trench area 21 than in the less dense trench area 22.
In FIG. 2d, an arsenic silicate glass (ASG) layer 209 is conformably formed as a bottom electrode of a capacitor on the exposed pad layer 203 and the exposed trenches 208.
In FIG. 2e, a photoresist layer is formed on the ASG layer 209, and the trenches 208 are filled with the ASG layer 209. The thickness of a photoresist layer 210a on the top surface of the dense trench area 21 is less than a photoresist layer 2310b on the less dense area 22 because there are more trenches 208 filled by the photoresist layer in the dense trench area 21.
In FIG. 2f, the photoresist layer 210a and 210b are etched to a predetermined depth in the trenches 208. Because a thickness of the photoresist layer 210a is thinner than the photoresist layer 210b, the photoresist layer 210a is removed before the photoresist layer 210b, and a height of a photoresist layer 210c in each trench 208 of the dense trench area 21 is lower than a photoresist layer 210d in each trench 208 of the less dense trench area 22.
In FIG. 2g, the ASG layer 209 is etched using the photoresist layer 210c and 210d as etching masks to leave an ASG layer 209a and 209b, and the ASG layer 209b is larger than the ASG layer 209a. 
In FIG. 2h, the photoresist layer 210c and 210d are removed.
In FIG. 2i, the semiconductor substrate 201 is annealed to diffuse As ions to form the ASG layer 209a and 209b to form an As doped area 211a and 211b as bottom electrodes in the semiconductor substrate 201. The ASG layer 209a and 209b are removed.
The sizes of the bottom electrodes of the trench capacitors of the dense trench area 21 are different from the less dense trench area 22 because the sizes of the As doped area 211a and 211b are not similar.